Intel Speeds AI Development, Deployment and Performance with New Class of AI Hardware from Cloud to Edge | Business Wire
How to Develop High-Performance Deep Neural Network Object Detection/Recognition Applications for FPGA-based Edge Devices - Embedded Computing Design
How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices - Blog - Company - Aldec
Processing AI at the Edge: GPU, VPU, FPGA, ASIC Explained - ADLINK Blog
Embedded deep learning creates new possibilities across disparate industries | Vision Systems Design
Deep Learning Accelerators Foundation IP| DesignWare IP| Synopsys
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
How to make your own deep learning accelerator chip! | by Manu Suryavansh | Towards Data Science
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
FPGA vs GPU for Machine Learning Applications: Which one is better? - Blog - Company - Aldec
Google AI Blog: Chip Design with Deep Reinforcement Learning
Arch-Net: A Family Of Neural Networks Built With Operators To Bridge The Gap Between Computer Architecture of ASIC Chips And Neural Network Model Architectures - MarkTechPost
Review of ASIC accelerators for deep neural network - ScienceDirect
Embedded Machine Learning
Processing AI at the Edge: GPU, VPU, FPGA, ASIC Explained - ADLINK Blog
Why ASICs Are Becoming So Widely Popular For AI
Deep learning on mobile devices: a review
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
Are ASIC Chips The Future of AI?
An on-chip photonic deep neural network for image classification | Nature
Deep Learning in Mining Biological Data | SpringerLink
The New Deep Learning Memory Architectures You Should Know About — eSilicon Technical Article | ChipEstimate.com
Hardware for Deep Learning. Part 4: ASIC | by Grigory Sapunov | Intento
FPGA Based Deep Learning Accelerators Take on ASICs
My take on the Gartner Hype Cycle | by Jens Møllerhøj | Medium
